H01L2224/0579

Semiconductor Chip Including Self-Aligned, Back-Side Conductive Layer and Method for Making the Same
20190096758 · 2019-03-28 ·

A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.

Semiconductor Chip Including Self-Aligned, Back-Side Conductive Layer and Method for Making the Same
20190096758 · 2019-03-28 ·

A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.

Light emitting device with buffer pads
10170455 · 2019-01-01 · ·

A light emitting device includes a carrier, a plurality of light emitting diode chips and a plurality of buffer pads. Each light emitting diode chip includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a via hole and a plurality of bonding pads. The via hole sequentially penetrates through the first type semiconductor layer, the active layer and a portion of the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the via hole define a epitaxial structure. The buffer pads are disposed between the carrier and the second type semiconductor layer, wherein the buffer pads is with Young's modulus of 210 GPa, the second bonding pad is disposed within the via hole to contact the second type semiconductor layer, and the epitaxial structure is electrically bonded to the receiving substrate through the bonding pads.

Light emitting device with buffer pads
10170455 · 2019-01-01 · ·

A light emitting device includes a carrier, a plurality of light emitting diode chips and a plurality of buffer pads. Each light emitting diode chip includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a via hole and a plurality of bonding pads. The via hole sequentially penetrates through the first type semiconductor layer, the active layer and a portion of the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the via hole define a epitaxial structure. The buffer pads are disposed between the carrier and the second type semiconductor layer, wherein the buffer pads is with Young's modulus of 210 GPa, the second bonding pad is disposed within the via hole to contact the second type semiconductor layer, and the epitaxial structure is electrically bonded to the receiving substrate through the bonding pads.

Semiconductor device and method of manufacturing thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

Semiconductor device and method of manufacturing thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

PROCESS FOR METALIZATION OF COPPER PILLARS IN THE MANUFACTURE OF MICROELECTRONICS

Features such as bumps, pillars and/or vias can be plated best using current with either a square wave or square wave with open circuit wave form. Using the square wave or square wave with open circuit wave forms of plating current, produces features such as bumps, pillars, and vias with optimum shape and filling characteristics. Specifically, vias are filled uniformly and completely, and pillars are formed without rounded tops, bullet shape, or waist curves. In the process, the metalizing substrate is contacted with an electrolytic copper deposition composition. The deposition composition comprises a source of copper ions, an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof, an accelerator, a suppressor, a leveler, and chloride ions.

PROCESS FOR METALIZATION OF COPPER PILLARS IN THE MANUFACTURE OF MICROELECTRONICS

Features such as bumps, pillars and/or vias can be plated best using current with either a square wave or square wave with open circuit wave form. Using the square wave or square wave with open circuit wave forms of plating current, produces features such as bumps, pillars, and vias with optimum shape and filling characteristics. Specifically, vias are filled uniformly and completely, and pillars are formed without rounded tops, bullet shape, or waist curves. In the process, the metalizing substrate is contacted with an electrolytic copper deposition composition. The deposition composition comprises a source of copper ions, an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof, an accelerator, a suppressor, a leveler, and chloride ions.

Wafer-level packaging sensing device and method for forming the same

A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.

Wafer-level packaging sensing device and method for forming the same

A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.