A semiconductor package includes a package substrate, a base module disposed on the package substrate and configured to include an intermediate chip, bonding wires connecting the intermediate chip to the package substrate, a lower-left chip disposed between the base module and the package substrate, and an upper-left chip disposed on the base module. The base module further includes an encapsulant encapsulating the intermediate chip, through vias electrically connected to the upper-left chip, and redistributed lines (RDLs) connecting the intermediate chip to the through vias and extending to provide connection parts which are spaced apart from the through vias and are connected to the lower-left chip.

According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen.

A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

An amplifier includes: a first transistor chip including a plurality of cells and provided beside an input matching substrate; a second transistor chip including a plurality of cells and provided beside the input matching substrate; a plurality of first bonding wires connecting the input matching substrate and the first transistor chip; and a plurality of second bonding wires connecting the input matching substrate and the second transistor chip, and variance of the mutual inductance of the first bonding wires and the second bonding wires is compensated by adjusting the self-inductance of the first bonding wires and the second bonding wires.

A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.

An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

In described examples, a method of printing repassivation onto a substrate includes depositing an ink comprising particles of a repassivation material onto specified locations on a surface of the substrate using an inkjet printer, and curing the repassivation material. The ink is deposited so that specified portions of the substrate surface are not covered by the ink

A stack package includes a package substrate having a bond finger and a stack of a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first pad, a second pad, and a first redistributed line connecting the first and second pads to each other. The second semiconductor die includes a third pad, a fourth pad, and a second redistributed line connecting the third and fourth pads to each other. The first and third pads are connected to each other by a first interconnector which is bonded to the bond finger, and the second and fourth pads are connected to each other by a second interconnector.