Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform.

Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.

Embodiments of the disclosure provide an optical sensing system and an optical sensing method thereof. The optical sensing system comprises a light source configured to emit an optical signal into an environment surrounding the optical sensing system. The optical sensing system further comprises a photodetector configured to receive the optical signal reflected from the environment of the optical sensing system, and convert the optical signal to an electrical signal, where the photodetector is disposed in a package. The optical sensing system additionally comprises a readout circuit configured to generate a readout signal based on the electrical signal received from the photodetector, where the readout circuit is disposed in the same package as the photodetector and connected to the photodetector through routings in the package.

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.

A display apparatus includes: a substrate; a plurality of sub-pixel circuits on the substrate, each of the plurality of sub-pixel circuits including at least one transistor; a plurality of light-emitting diodes electrically connected to the plurality of sub-pixel circuits, respectively, and defining a display area; a pad at a non-display area outside the display area; a conductive line extending toward a first edge of the substrate; and a conductor electrically connecting the conductive line to the pad. The conductor overlaps with the pad, is interposed between a part of the conductive line and a part of the pad, and has an isolated shape in a plan view.

An electronic device is provided. The electronic device includes a substrate, a plurality of first pads, a plurality of second pads, a first data line and a touch signal line. The substrate has a first bonding area and a second bonding area. The first pads are disposed in the first bonding area and arranged along a first direction. The second pads are disposed in the second bonding area and arranged along a second direction. There is an included angle between the first direction and the second direction. The first data line is disposed on the substrate and electrically connected to at least one of the first pads or the second pads. The touch signal line is disposed on the substrate and electrically connected to at least another one of the first pads or the second pads. The first data line at least partially overlaps the touch signal line.

Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.