An array substrate (100, 200, 300) comprises a display region (110) and a bonding region (130, 230, 330). The bonding region (130, 230, 330) is disposed around the display region (110). The bonding region (130, 230, 330) of the array substrate (100, 200, 300) is provided with at least one pad (150, 250). The at least one pad (150, 250) comprises a plurality of first gold fingers (151, 251, 351) spaced apart and arranged in parallel. Intervals between adjacent first golden fingers (151, 251, 351) in the same pad (150, 250) are not entirely the same.

A display device includes a display panel, a first film attached to the display panel, an adhesive member interposed between the display panel and the first film and extending in a first direction to attach the display panel to the first film, a first test electrode covered by the adhesive member; a second test electrode covered by the adhesive member and spaced apart from the first test electrode in a second direction perpendicular to the first direction, and test lines comprising a first test line electrically connected to the first test electrode and a second test line electrically connected to the second test electrode, where the adhesive member is disposed between the first test electrode and the second test electrode in the second direction.

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

A device substrate comprising a substrate, a first pad, a second pad, a plurality of first power lines, a plurality of second power lines, and a plurality of control units is provided. The first pad is disposed on the first side of the device substrate. The second pad is disposed on the second side of the device substrate. The second side is opposite the first side. The first power lines are electrically connected to the first pad. The second power lines are electrically connected to the second pad. The control unit is electrically connected to at least one of the first power line and the second power line. The first pad does not overlap the second pad in a first direction perpendicular to the first side or in a second direction perpendicular to the second side. A display panel is also provided. A tiled display is also provided.

Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

A semiconductor device includes a switching element, a control element that controls the switching element, an island lead on which the switching element and the control element are mounted, and a plurality of terminal leads. The switching element includes a first electrode, a second electrode and a third electrode, where the first electrode and the second electrode are offset from the third electrode in a first sense of a thickness direction. The island lead has an obverse surface facing in the first sense of the thickness direction and supporting the switching element and the control element. Each terminal lead is electrically connected to the second electrode or the control element. The island lead is spaced apart from the plurality of terminal leads.

A multichip module comprises a carrier, a plurality of chips, an electrical insulating layer, and an electrical interconnect structure. The carrier includes a bottom wall and four side walls defining an internal cavity. The chips are positioned in the internal cavity, with each chip including a plurality of bond pads. The electrical insulating layer is formed from electrically insulating material and is positioned on an upper surface of the carrier and the chips. The electrical interconnect structure includes a plurality of interconnect traces, with each interconnect trace formed from electrically conductive material and electrically connected to a first bond pad on a first chip and a second bond pad on a second chip. Each interconnect trace includes a bridge having a segment that is spaced apart from, and positioned above, the electrical insulating layer.

A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

An image sensor package including an image sensor chip including an active pixel sensor region and a non-sensing region, a plurality of chip pads being in the non-sensing region; a printed circuit board on one side of the image sensor chip, the printed circuit board including a plurality of bonding pads; conductive wires respectively connecting the plurality of chip pads to the plurality of bonding pads; a bonding dam at a periphery of the active pixel sensor region; a cover glass on the bonding dam and facing another side of the image sensor chip; and an encapsulation layer covering a side surface of the bonding dam, a side surface of the cover glass, an edge of a lower surface of the cover glass, the non-sensing region, and an edge of an upper surface of the printed circuit board, wherein the bonding dam is spaced apart from an end of a side surface of the image sensor chip by a distance of 80 μm to 150 μm has a height of 50 μm to 150 μm from the image sensor chip, and has a width of 160 μm to 240 μm.