A method includes forming integrated circuit devices on a semiconductor substrate of a wafer, forming a voltage regulator in the wafer, and forming a metal layer as a part of the wafer. A transistor is formed farther away from the semiconductor substrate than the metal layer. The transistor includes a first source/drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source/drain region to a second voltage that is lower than the first voltage, and provide the second voltage to the integrated circuit devices. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

A semiconductor package is configured for electrically connecting an external component to a top surface of the semiconductor package. The semiconductor package includes a raised connector that extends from a lead frame portion, vertically through encapsulation material, and is exposed at the top surface. A semiconductor component is electrically connected to the lead frame portion. The raised connector includes a vertical column and a horizontal pad, contiguous with each other. The raised connector has a continuous core, which is electrically conductive, extending throughout the vertical column and throughout the horizontal pad. The vertical column is attached to the lead frame portion. A top surface of the horizontal pad is exposed at a top surface of the encapsulation material. The raised connector may include two or more vertical columns. The semiconductor package may include two or more raised connectors, each attached to the lead frame portion.

An electronic assembly is disclosed. The electronic assembly can include a first integrated device package having a first substrate, a plurality of electronic components mounted to the first substrate, a first plurality of vertical interconnects connected to first substrate and extending outwardly, a first molding compound over at least portions of the plurality of electronic components, and an electromagnet connected to the first substrate. The electromagnet can be connected to the plurality of electronic components via one or more electrical connections. The electronic assembly can also include a second integrated device package having a second substrate, a second plurality of vertical interconnects connected to the second substrate, a second molding compound, and electrical terminals formed on a second side of the second substrate. The first and second vertical interconnects can be disposed between the first and second substrates.

A package structure includes a device structure and a wafer structure. The wafer structure is bonded to the device structure. The device structure includes a device die, a first redistribution layer, first hybrid bonds, and first shield portions. The first redistribution layer is disposed on the device die. The first hybrid bonds are electrically connected to the first redistribution layer. The first shield portions peripherally cover the first hybrid bonds for electromagnetic interference (EMI) shielding. The wafer structure includes a wafer substrate, a second redistribution layer, second hybrid bonds, and second shield portions. The second redistribution is disposed on the wafer substrate. The second hybrid bonds are respectively connected to the first hybrid bonds and the second redistribution layer. The second shield portions are connected to the first shield portions and the second redistribution layer. The second shield portions peripherally cover the second hybrid bonds for EMI shielding.

This application is directed to monitoring a package of an electronic device (e.g., a memory device including a solid state drive (SSD)). The electronic device includes a package substrate, a package, and an interface circuit. The package substrate includes one or more connectors. The package includes a plurality of electrodes that are exposed on a top surface of the package and electrically coupled to the one or more connectors. The interface circuit is coupled to the one or more connectors of the package substrate, and configured to measure one or more electrical signals via the one or more connectors of the package substrate and determine one or more interface parameters of the top surface of the package based on the one or more electrical signals. The package is physically coupled to the package substrate and configured to enclose and protect an integrated circuit (e.g., including the interface circuit).

Embodiments disclosed herein comprise an apparatus. In an embodiment, the apparatus comprises a substrate with a first cavity into the substrate. In an embodiment, the first cavity has a first depth. In an embodiment, a second cavity is provided into the substrate, where the second cavity has a second depth that is different than the first depth. In an embodiment, a first die is in the first cavity, where the first die has a first thickness. In an embodiment, a second die is in the second cavity, where the second die has a second thickness that is different than the first thickness.

An electrical device that includes a stacked semiconductor device structure connected to a device substrate through a sidewall interconnect. The sidewall interconnect of the stacked semiconductor device structure is in contact with metal lines extending from a sidewall of the stacked semiconductor device structure to semiconductor devices positioned within an interior the stacked semiconductor device structure. The electrical device includes a heat spreader connected to the stacked semiconductor structure.

An integrated circuit (IC) including a die is described. The die is composed of an active device layer and interconnect layers coupled to the active device layer. The IC also includes an active power distribution network (PDN) layer. The active PDN layer includes a power switch and an intermetal dielectric (IMD) layer. The IMD metal layer is coupled between the power switch and the die.

A semiconductor package includes a carrier having a die pad and a plurality of leads, a first discrete power device die mounted on the die pad and having a first load terminal pad disposed on a main surface that faces away from the die pad, a first package load terminal formed by one or more of the leads, and a first metal clip that electrically connects the first load terminal pad of the first discrete power device die with the first package load terminal, wherein the first metal clip comprises a local constriction that is configured to locally reduce a heat conductance of the first metal clip in a section of the first metal clip that is between the first discrete power device die and the first package load terminal.

A method for manufacturing and testing a semiconductor package includes receiving a first semiconductor structure having a first side and a second side opposite to the first side, wherein the first semiconductor structure further includes: a first die; a first bump disposed over the first die; a first via adjacent to the first die; and a first molding surrounding the first die, the first bump and the first via. The method further includes disposing a plurality of connectors on the first side, wherein each of the plurality of connectors is electrically connected to at least one of the first bump and the first via; probing the plurality of connectors; and bonding the first semiconductor structure to a second semiconductor structure, wherein the plurality of connectors are disposed between the first semiconductor structure and the second semiconductor structure after the bonding.