A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.

A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.

In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area; a fan-in chip structure located in the through-hole, the fan-in chip structure comprising a first chip, a capacitor chip arranged to be apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip; a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.

The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.

A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.