A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.

A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.

A semiconductor package includes: a substrate including an insulating layer, a plurality of pads on the insulating layer, a surface protective layer covering the insulating layer and having first through-holes exposing at least a portion of the insulating layer and second through-holes exposing at least a portion of each of the plurality of pads, a plurality of first dummy patterns extending from the plurality of pads to the first through-holes, and a plurality of second dummy patterns extending from the first through-holes to an edge of the insulating layer; a semiconductor chip on the substrate and including connection terminals electrically connected to the plurality of pads exposed through the second through-holes; and an encapsulant encapsulating at least a portion of the semiconductor chip and filling the first through-holes, wherein a separation distance between the first through-holes is greater than a separation distance between the second through-holes.

Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Apparatus and methods are disclosed for transferring solder to a substrate. A substrate belt moves one or more substrates in a belt direction. A decal has one or more through holes in a hole pattern that hold solder. Each of the solder holes can align with respective locations on one of the substrates. An ultrasonic head produces an ultrasonic vibration in the solder in a longitudinal direction perpendicular to the belt direction. The ultrasonic head and substrate can be moved together in the longitudinal direction to maintain the ultrasonic head in contact with the solder while the ultrasonic head applies the ultrasonic vibration. Various methods are disclosed including methods of transferring the solder with or without external heating.

Apparatus and methods are disclosed for transferring solder to a substrate. A substrate belt moves one or more substrates in a belt direction. A decal has one or more through holes in a hole pattern that hold solder. Each of the solder holes can align with respective locations on one of the substrates. An ultrasonic head produces an ultrasonic vibration in the solder in a longitudinal direction perpendicular to the belt direction. The ultrasonic head and substrate can be moved together in the longitudinal direction to maintain the ultrasonic head in contact with the solder while the ultrasonic head applies the ultrasonic vibration. Various methods are disclosed including methods of transferring the solder with or without external heating.

A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.

A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.