A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.

A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.

The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.

The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.

Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

Techniques regarding forming flip chip interconnects are provided. For example, one or more embodiments described herein can comprise a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology. The three-dimensionally printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

Techniques regarding forming flip chip interconnects are provided. For example, one or more embodiments described herein can comprise a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology. The three-dimensionally printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

A temporary chip assembly, a display panel, and manufacturing methods of the temporary chip assembly and the display panel are provided. In the display panel, welding points between a micro light-emitting chip and corresponding bonding pads on a display backboard are covered with pyrolytic adhesive to block water and oxygen, thereby slowing down or avoiding the oxidation of the welding points.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.