An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.

An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.