A detection method and a detection structure for a display backplane is provided in the disclosure. The detection method includes the following. The display backplane is provided. The display backplane is provided with a contact electrode pair. A detection structure is provided. The detection structure includes a light-emitting element and a detection circuit configured to conduct an electrical signal to the light-emitting element. The detection structure is assembled on the display backplane to connect the detection circuit to the contact electrode pair. A drive electrical signal is outputted to the contact electrode pair. If the light-emitting element does not emit light, the contact electrode pair is determined as a fault point.

A detection method and a detection structure for a display backplane is provided in the disclosure. The detection method includes the following. The display backplane is provided. The display backplane is provided with a contact electrode pair. A detection structure is provided. The detection structure includes a light-emitting element and a detection circuit configured to conduct an electrical signal to the light-emitting element. The detection structure is assembled on the display backplane to connect the detection circuit to the contact electrode pair. A drive electrical signal is outputted to the contact electrode pair. If the light-emitting element does not emit light, the contact electrode pair is determined as a fault point.

A semiconductor composite structure includes an electrically conductive bump, and a patterned bonding layer. The electrically conductive bump includes a body portion for being electrically connected to a metal layer of a semiconductor substrate, and a contact portion disposed on the body portion opposite to the metal layer. The patterned bonding layer is disposed on the contact portion opposite to the body portion, and includes an electrically conductive portion and a recess portion depressed relative to the electrically conductive portion. An etching selectivity ratio of the conductive portion relative to the contact portion is greater than 1. A method for making the semiconductor composite structure and a semiconductor device are also disclosed.

A semiconductor composite structure includes an electrically conductive bump, and a patterned bonding layer. The electrically conductive bump includes a body portion for being electrically connected to a metal layer of a semiconductor substrate, and a contact portion disposed on the body portion opposite to the metal layer. The patterned bonding layer is disposed on the contact portion opposite to the body portion, and includes an electrically conductive portion and a recess portion depressed relative to the electrically conductive portion. An etching selectivity ratio of the conductive portion relative to the contact portion is greater than 1. A method for making the semiconductor composite structure and a semiconductor device are also disclosed.

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.