A method for bonding two superconducting integrated circuits (chips), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

A method for bonding two superconducting integrated circuits (chips), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

An electronic component with high coplanarity, including a body with a functional circuit and a mounting plane, a first electrode with a first area deposited on the mounting plane, and a second electrode with a second area deposited on the mounting plane, wherein the first area is larger than the second area, and the first electrode and the second electrode includes a conductive layer and at least one first plating layer over the conductive layer, and a thickness of the conductive layer of the first electrode is smaller than a thickness of the conductive layer of the second electrode, and a thickness of the first plating layer of the first electrode is larger than a thickness of the first plating layer of the second electrode.

An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.

A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.