An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

The present disclosure relates to a technology relating to a power semiconductor module of which heat is dissipated through both sides thereof and provides a technology for maintaining a distance between an upper substrate and a lower substrate by a metal bump formed on one side of a power semiconductor die.

A power semiconductor apparatus includes a conductive circuit pattern, a power semiconductor device, a sealing member, a conductive post, and a conductive post. A first conductive post is connected to the conductive circuit pattern. A second conductive post is connected to the power semiconductor device. The first conductive post includes a metal pin and a conductive bonding member. The conductive post includes a metal pin and a conductive bonding member.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects.

A representative system and method for manufacturing stacked semiconductor devices includes disposing an aqueous alkaline solution between a first semiconductor device and a second semiconductor device prior to bonding. In a representative implementation, first and second semiconductor devices may be hybrid bonded to one another, where dielectric features of the first semiconductor device are bonded to dielectric features of the second semiconductor device, and metal features of the first semiconductor device are bonded to metal features of the second semiconductor device. Immersion bonds so formed demonstrate a substantially lower incidence of delamination associated with bond defects.

Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present disclosure includes a wiring including a plurality of layers including an insulating layer and a wiring layer, a semiconductor chip mounted on the wiring and electrically connected to the wiring layer through a bonding pad, a cover member configured to cover side surfaces of the semiconductor chip and the wiring and be in contact with at least one wiring layer, and an encapsulant configured to seal the cover member. Accordingly, the cover member covers the semiconductor chip and is in contact with the wiring formed under the semiconductor chip, thereby reducing electromagnetic interference, minimizing noise between operations of the semiconductor package, and improving a signal speed

Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present disclosure includes a wiring including a plurality of layers including an insulating layer and a wiring layer, a semiconductor chip mounted on the wiring and electrically connected to the wiring layer through a bonding pad, a cover member configured to cover side surfaces of the semiconductor chip and the wiring and be in contact with at least one wiring layer, and an encapsulant configured to seal the cover member. Accordingly, the cover member covers the semiconductor chip and is in contact with the wiring formed under the semiconductor chip, thereby reducing electromagnetic interference, minimizing noise between operations of the semiconductor package, and improving a signal speed

A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.