Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.

This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.

In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.

A semiconductor package of a pin-grid-array type includes a bump pad on a first substrate, a metal socket on a second substrate, a core material for reverse reflow on the bump pad, and solder paste or a solder bump forming a solder layer on the core material for reverse reflow. The solder paste or the solder bump is in contact with the bump pad. The core material for reverse reflow and the solder paste or the solder bump bonded to the core material for reverse reflow are used as a pin and detachably attached to the metal socket. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.