The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

An electrically conductive pillar that can bond a base member and a member to be bonded together with high bonding strength with a bonding layer interposed therebetween and a method for manufacturing the same. Specifically, an electrically conductive pillar 1 is composed of a sintered body 12 of metal micro-particles disposed on a base member 11. The average particle size of the metal micro-particles is less than 1 μm as measured using a small-angle X-ray scattering method. An upper surface 12b of the sintered body 12 has a concave shape recessed on the base member 11 side. The metal micro-particles are preferably made of one or more metals selected from Ag and Cu.

A bonding structure, a package structure, and a method for manufacturing a package structure are provided. The package structure includes a first substrate, a first passivation layer, a first conductive layer, and a first conductive bonding structure. The first passivation layer is disposed on the first substrate and has an upper surface. The first passivation layer and the first substrate define a first cavity. The first conductive layer is disposed in the first cavity and has an upper surface. A portion of the upper surface of the first conductive layer is below the upper surface of the first passivation layer. The first conductive bonding structure is disposed on the first conductive layer.

A bonding structure, a package structure, and a method for manufacturing a package structure are provided. The package structure includes a first substrate, a first passivation layer, a first conductive layer, and a first conductive bonding structure. The first passivation layer is disposed on the first substrate and has an upper surface. The first passivation layer and the first substrate define a first cavity. The first conductive layer is disposed in the first cavity and has an upper surface. A portion of the upper surface of the first conductive layer is below the upper surface of the first passivation layer. The first conductive bonding structure is disposed on the first conductive layer.

A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.

The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.

The present disclosure relates to a fabrication process of a semiconductor chip, which starts with providing a precursor wafer mounted on a carrier. The precursor wafer includes a precursor substrate and component portions between the carrier and the precursor substrate. The precursor substrate is then thinned down to provide a thinned substrate, which includes a substrate base adjacent to the component portions and an etchable region over the substrate base. Next, the etchable region is selectively etched to generate a number of protrusions over the substrate base. Herein, the substrate base is retained, and portions of the substrate base are exposed through the protrusions. Each protrusion protrudes from the substrate base and has a same height. A metal layer is then applied to provide a semiconductor wafer. The metal layer selectively covers the exposed portions of the substrate base and covers at least a portion of each protrusion.

The present disclosure relates to a fabrication process of a semiconductor chip, which starts with providing a precursor wafer mounted on a carrier. The precursor wafer includes a precursor substrate and component portions between the carrier and the precursor substrate. The precursor substrate is then thinned down to provide a thinned substrate, which includes a substrate base adjacent to the component portions and an etchable region over the substrate base. Next, the etchable region is selectively etched to generate a number of protrusions over the substrate base. Herein, the substrate base is retained, and portions of the substrate base are exposed through the protrusions. Each protrusion protrudes from the substrate base and has a same height. A metal layer is then applied to provide a semiconductor wafer. The metal layer selectively covers the exposed portions of the substrate base and covers at least a portion of each protrusion.