A Cu core ball and a method of manufacturing such a Cu core ball. Purity of the Cu internal ball is at least 99.9% and not greater than 99.995%. A total contained amount of Pb and/or Bi in impurity contained in the Cu ball is equal to or larger than 1 ppm. Its sphericity is at least 0.95. A solder plating film coated on the Cu ball is of Sn solder or a lead free solder alloy whose primary component is Sn. In the solder plating film, a contained amount of U is not more than 5 ppb and that of Th is not more than 5 ppb. A total alpha dose of the Cu ball and the solder plating film is not more than 0./0200 cph/cm2. An arithmetic average roughness of the Cu core ball is equal to or less than 0.3 m.

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 m). The subarray probe tips may be on a pitch at or less than fifty microns (50 m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 m). The subarray probe tips may be on a pitch at or less than fifty microns (50 m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.