Patent classifications
H01L2224/1366
Planarity-tolerant reworkable interconnect with integrated testing
A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.
Semiconductor packages
Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.
Semiconductor packages
Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.
Bump electrode, board which has bump electrodes, and method for manufacturing the board
A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01 C./sec and less than 0.3.
Bump electrode, board which has bump electrodes, and method for manufacturing the board
A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01 C./sec and less than 0.3.
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO REDUCE INTERMETALLIC COMPOUND FORMATION IN INTEGRATED CIRCUIT PACKAGES
Methods, systems, apparatus, and articles of manufacture to reduce intermetallic compound formation in integrated circuit packages are disclosed. An example package substrate includes a buildup layer including a metal pad, an interconnect bridge embedded in the buildup layer, the interconnect bridge including a first contact pad on a first side of the interconnect bridge and a second contact pad on a second side of the interconnect bridge, the second side opposite the first side, and solder positioned between the metal pad and the first contact pad, the solder to electrically couple the metal pad and the first contact pad, a weight percent of nickel in any layer of material between the metal pad and the first contact pad being less than a threshold.