A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.

A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.

A bonding electrode structure of a flip-chip LED chip includes: a substrate; a light-emitting epitaxial layer over the substrate; a bonding electrode over the light-emitting epitaxial layer, wherein the bonding electrode structure includes a metal laminated layer having a bottom layer and an upper surface layer from bottom up. The bottom layer structure is oxidable metal and the side wall forms an oxide layer. The upper surface layer is non-oxidable metal. The bonding electrode structure has a main contact portion, and a grid-shape portion surrounding the main contact portion in a horizontal direction. The problems during packaging and soldering of the flip-chip LED chip structure, such as short circuit or electric leakage, can thus be solved.

A bonding electrode structure of a flip-chip LED chip includes: a substrate; a light-emitting epitaxial layer over the substrate; a bonding electrode over the light-emitting epitaxial layer, wherein the bonding electrode structure includes a metal laminated layer having a bottom layer and an upper surface layer from bottom up. The bottom layer structure is oxidable metal and the side wall forms an oxide layer. The upper surface layer is non-oxidable metal. The bonding electrode structure has a main contact portion, and a grid-shape portion surrounding the main contact portion in a horizontal direction. The problems during packaging and soldering of the flip-chip LED chip structure, such as short circuit or electric leakage, can thus be solved.

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3) electrically connected to the bump electrode (2), and a resin encapsulation body (6) covering the semiconductor chip (1), the bump electrode (2), and the conductive layer (3). On a back surface of the semiconductor chip (1) that is flush with a back surface of the resin encapsulation body (6), a metal layer (4) and a laminated film (5) are formed. The laminated film (5) is formed on a front surface of the conductive layer (3). The external terminal (9) is arranged on an inner side of an outer edge of the semiconductor chip (1).

Disclosed is a solder particle including a plastic core; a copper-free metal layer which is formed on an external surface of the plastic core; and a solder layer which is formed on the copper-free metal layer and contains not less than 85 wt % tin. Thus, it is possible to provide a solder particle with a copper-free metal layer, which is excellent in strength and conductivity and prevents or minimizes generation of a void during a reflow process or the like.