A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.

Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

Connection terminals of a semiconductor module are disposed appropriately in accordance with the connection destination of the semiconductor module. A semiconductor module which includes at least one semiconductor element is mounted on a first surface of a main substrate, which has the first surface on which a first circuit element is mounted and a second surface on which a second circuit element is mounted. A plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate. The first connection terminal group is disposed on the outer peripheral side with respect to the second connection terminal group.

Semiconductor devices having mechanical pillar structures, such as angled pillars, that are rectangular and oriented with respect to a semiconductor die to reduce bending stress and in-plane shear stress at a semiconductor die to which the angled pillars are attached, and associated systems and methods, are disclosed herein. The semiconductor device can include angled pillars coupled to the semiconductor die and to a package substrate. The angled pillars can be configured such that they are oriented relative to a direction of local stress to increase section modulus.

Semiconductor devices having mechanical pillar structures, such as angled pillars, that are rectangular and oriented with respect to a semiconductor die to reduce bending stress and in-plane shear stress at a semiconductor die to which the angled pillars are attached, and associated systems and methods, are disclosed herein. The semiconductor device can include angled pillars coupled to the semiconductor die and to a package substrate. The angled pillars can be configured such that they are oriented relative to a direction of local stress to increase section modulus.

A piezoelectric vibrator that includes a piezoelectric resonator, a substrate having opposite first and second principal surfaces, and an electrically conductive holding member holding the piezoelectric resonator on the first principal surface of the substrate such that the piezoelectric resonator is able to be excited. The electrically conductive holding member contains a first filler containing an electrically conductive material as a main component and a second filler containing an electrically insulating material as a main component and having a smaller Young's modulus than the first filler. In a plan view in a direction normal to the first principal surface of the substrate, the second filler is more densely disposed in an outer peripheral region of the electrically conductive holding member than in a central region of the electrically conductive holding member.

A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area.

A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.