A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.

An electronic device and a layout checking method are provided. The electronic device includes a base and a semiconductor device. The base has a top surface and a bottom surface opposite to the tope surface. The semiconductor device is disposed on the top surface of the base. The semiconductor device has a device edge located within the base in a top view. The base includes at least two groups of ground vias disposed on the base and close to the top surface. The at least two groups of ground vias are arranged symmetrically with a first type of symmetry, and each of the least two groups of ground vias comprises at least three first ground vias arranged symmetrically with a second type of symmetry.