A display panel includes a substrate composed of a plurality of pixels; and a plurality of integrated circuits (ICs) disposed on a top surface of the substrate, each IC including a plurality of IC pads and the substrate including a plurality of substrate pads corresponding to the IC pads and disposed on the top surface of the substrate. In one embodiment, the ICs are bonded on the substrate via the IC pads and the substrate pads, which are interconnected by laser as a heat source. In another embodiment, each IC is disposed above to cover up at least one pixel.

The present disclosure provides an array substrate and a fabrication method thereof, a display panel and a display module. The array substrate has a display region and a bonding region for bonding with a circuit board, and including: a data line and a gate line in the display region; and a bump unit in the bonding region. The bump unit includes: a gate line bump layer, which is in a same layer and made of a same material as the gate line, is connected to the data line, and includes a main body portion and a plurality of hollowed-out portions in the main body portion; and a data line bump layer, which is in a same layer and made of a same material as the data line, and covers the main body portion and the plurality of hollowed-out portions of the gate line bump layer.

A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.

A semiconductor package structure includes a substrate having a patterned surface, the patterned surface including a first region and a second region, wherein a first line width in the first region is smaller than a second line width in the second region. The semiconductor package structure further includes a first die hybrid-bonded to the first region through conductive features adapted for the first line width, and a second die bonded to the second region through conductive features adapted for the second line width. The manufacturing operations of the semiconductor package structure are also disclosed.

Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.

Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.

A semiconductor device comprising: substrate having main surface facing thickness direction; wirings arranged on main surface; semiconductor element having back surface facing the main surface and electrodes formed on back surface, wherein the electrodes are bonded to the wirings; and columnar wirings located outside the semiconductor element as viewed along the thickness direction, protrude in direction away from the main surface in the thickness direction, and are arranged on the wirings, wherein the semiconductor element includes first circuit and second circuit, wherein the electrodes include first electrodes electrically connected to the first circuit and second electrodes electrically connected to the second circuit, wherein the columnar wirings include first columnar portions electrically connected to the first electrodes and second columnar portions electrically connected to the second electrodes, and wherein area of each first columnar portions is larger than area of each second columnar portions in the thickness direction.

Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.