Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/10
Bump connectors; Manufacturing methods related thereto
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H01L2224/12
Structure, shape, material or disposition of the bump connectors prior to the connecting process
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H01L2224/14
of a plurality of bump connectors
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H01L2224/1416
Random layout, i.e. layout with no symmetry
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H01L2224/14164
covering only portions of the surface to be connected
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H01L2224/14165
Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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H01L2224/14165

Semiconductor device including asymmetric electrode arrangement
09585197 · 2017-02-28 · ·

Provided is a semiconductor device including an asymmetric electrode arrangement in which a plurality of electrodes are arranged asymmetrically in a vertical or horizontal direction.