Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.

A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture 5 being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planar view is smallest among a plurality of areas of the through-hole in a planar view, a filler arranged within the 10 through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Package structures and methods for manufacturing the same are provided. The package structure includes a first substrate and through vias formed through the first substrate. The package further includes redistribution layers formed over the first substrate and connected to the through vias and a first pillar layer formed over the redistribution layers. The package further includes a first barrier layer formed over the first pillar layer and a first cap layer formed over the first barrier layer. The package further includes an underfill layer formed over the redistribution layers and surrounding the first pillar layer, the first barrier layer, and the first cap layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first sidewall surface of the first pillar layer and a second sidewall surface of the first cap layer.

A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.