An electronic substrate includes: a body having a mounting surface; an electronic component having an opposed surface facing the mounting surface; and an adhesive layer that bonds the electronic component to the mounting surface. The mounting surface has a storage recess that stores at least a part of the adhesive layer. The storage recess is located from a first area overlapping the opposed surface to a second area not overlapping the opposed surface in plan view.

A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.

A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.

A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

Reliability of joining between semiconductor chips is improved by promoting filling of a sealing resin into a gap formed between the semiconductor chips. A semiconductor device includes: a first semiconductor chip, which has a plurality of first electrodes on a surface; a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which includes an inner peripheral area that has a plurality of second electrodes connected to each of the first electrodes on a surface and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than the thickness of the inner peripheral area; and a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area.

A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.

A control unit that controls a motor includes a semiconductor device, the semiconductor device includes a semiconductor package including a plurality of first electrodes, a wiring board including a plurality of second electrodes arranged so as to correspond to each of the plurality of first electrodes, and solder joints connecting the plurality of first electrodes and the plurality of second electrodes, and a tip end of a second electrode arranged at an outermost corner of the wiring board is located outside an outer peripheral end of the semiconductor package.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.

A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.