A method for forming a conductive structure is disclosed, the method comprising the steps of: forming a metallic frame having a plurality of metal parts separated from each other; forming an insulating layer on the top surface of the plurality of metal parts; and forming a conductive pattern layer on the insulating layer for making electrical connections with at least one portion of the plurality of metal parts.

A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.

A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.

A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.

A package structure comprises: a plurality of metal parts, wherein each metal part is made of metal and each two adjacent metal parts are spaced apart by a gap being filled with an insulating material; a first insulating layer, disposed over a top of the plurality of metal parts and the top surface of a conductive element; and a first conductive layer, disposed over the first insulating layer, wherein a first conductive pattern electrically connects a first terminal of the conductive element to a first metal part through at least one first via disposed in the first insulating layer, wherein a bump is disposed in the first insulating layer and electrically connected to a second terminal of the conductive element.

A semiconductor device package includes a carrier, an electronic component, a protection layer, a conductive layer and an integrated passive device (IPD). The electronic component is disposed on the carrier. The protection layer covers the carrier and the electronic component. The conductive layer is disposed on the protection layer and penetrates the protection layer to be electrically connected to the electronic component. The IPD is disposed on the conductive layer and electrically connected to the electronic component through the conductive layer.

A package structure for a semiconductor device includes a first conductive layer, a second conductive layer, a first die, a second die, a plurality of first blind via pillars and a conductive structure. The first conductive layer has a first surface and a second surface. The first die and the second die respectively have an active surface and a back surface, which are disposed opposite to each other. There is a plurality of metal pads disposed on the active surface. The first die is attached to the first surface of the first conductive layer with its back surface, and the second die is attached to the second surface of the first conductive layer with its back surface. The first and second conductive layers, the first and second dies, the first blind hole pillars and conductive structure are covered by a dielectric material.

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.

A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.