A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

A packaging process of an electronic component is provided. By the packaging process of the disclosure, the electronic component is grinded by the back grinding process. Consequently, thickness of the electronic component may be reduced to less than or equal to 50 m. The packaging process may achieve ultra-thin thickness and reduce the space of the power module. Moreover, the packaging process forms the contact pads with drilling process and grinding process without photolithography process. Consequently, the packaging process is advantageous because of lower cost and uniform thickness of the contact pads.

Laser direct structuring, LDS material is molded onto semiconductor dice arranged on die pads in a leadframe and the semiconductor dice are electrically coupled with electrically conductive leads in the leadframe via electrical connections that comprise electrically conductive formations exposed at the front surface of the LDS material, electrically conductive vias between the semiconductor dice and the front surface of the LDS material, as well as electrically conductive lines over the front surface of the LDS material that couple selected ones of the electrically conductive formations with selected ones of the second electrically conductive vias. The electrically conductive vias and lines are provided applying laser beam energy to the front surface of the laser direct structuring material at spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material acting as fiducials. The electrically conductive formations exposed at the front surface of the LDS material may comprise pillar-like extensions of the leadframe leads, electrically conductive material grown on the leads in cavities in the front surface of the LDS material or electrically conductive leads in a lead frame where the die pads are downset with respect to the leads.

A packaging process of an electronic component is provided. By the packaging process of the disclosure, the electronic component is grinded by the back grinding process. Consequently, thickness of the electronic component may be reduced to less than or equal to 50 m. The packaging process may achieve ultra-thin thickness and reduce the space of the power module. Moreover, the packaging process forms the contact pads with drilling process and grinding process without photolithography process. Consequently, the packaging process is advantageous because of lower cost and uniform thickness of the contact pads.

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

A method of manufacturing an interconnect packaging structure is provided. In one aspect, the method includes forming a first body defining a cavity around at least one integrated circuit using an additive manufacturing machine, depositing a conductive transmission line on the first body and electrically coupling the conductive transmission line and the at least one integrated circuit with a conductive interconnect.

A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.

A package comprises a platform and at least one pedestal positioned along at least a portion of a perimeter of the platform. The platform and the at least one pedestal form a cavity. The package further comprises a die positioned in the cavity and on the platform, with the die having an active circuit facing away from the platform. The package also comprises a conductive layer coupled to the die and to a conductive terminal. The conductive terminal is positioned above the at least one pedestal, and the die and the conductive terminal are positioned in different horizontal planes.

A method produces a plurality of optoelectronic modules, and includes: A) providing a metallic carrier assembly with a plurality of carrier units; B) applying a logic chip, each having at least one integrated circuit, to the carrier units; C) applying emitter regions that generate radiation, which can be individually electrically controlled; D) covering the emitter regions and the logic chips with a protective material; E) overmolding the emitter regions and the logic chips so that a cast body is formed, which joins the carrier units, the logic chips and the emitter regions to one another; F) removing the protective material and applying electrical conductor paths to the upper sides of the logic chips and to a cast body upper side; and G) dividing the carrier assembly into the modules.

Embodiments of a method for packaging Integrated Circuit (IC) dies and an IC device are described. In an embodiment, a method for packaging IC dies involves creating openings on a substrate, where side surfaces of the openings on the substrate are covered by metal layers, placing the IC dies into the openings on the substrate, applying a second metal layer to the substrate, where the IC dies are electrically connected to at least a portion of the second metal layer, and cutting the substrate into IC devices.