A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component. A depth of the first recess is different from a depth of the second recess. A third recess is over a surface of the first electrical component. A depth of the third recess is different from the depth of the first recess and the depth of the second recess. A second electrical component is disposed over the leadframe. The clip bond extends over the second electrical component.

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

A lead frame for a hermetic RF chip package includes: a first capacitor unit formed of a conductive material in a rectangular shape having a width smaller than a length to receive an input of an RF signal applied to the package circuit; a first inductor unit connected to the first capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length; a second capacitor unit connected to the first inductor unit and formed of a conductive material in a rectangular shape having a width smaller than a length; and a second inductor unit connected to the second capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length to transfer an RF signal input through the first capacitor unit to the RF chip.

A lead frame for a hermetic RF chip package includes: a first capacitor unit formed of a conductive material in a rectangular shape having a width smaller than a length to receive an input of an RF signal applied to the package circuit; a first inductor unit connected to the first capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length; a second capacitor unit connected to the first inductor unit and formed of a conductive material in a rectangular shape having a width smaller than a length; and a second inductor unit connected to the second capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length to transfer an RF signal input through the first capacitor unit to the RF chip.

An optical module includes: an optical semiconductor device in which a semiconductor laser and an optical modulator are integrated; a bypass capacitor including a lower electrode and an upper electrode, the bypass capacitor being connected in parallel to the semiconductor laser; a dielectric substrate having an upper surface and a lower surface, the optical semiconductor device and the bypass capacitor being surface-mounted on the upper surface, the dielectric substrate having a conductor pattern on the upper surface, the cathode electrode and the lower electrode being bonded to the conductor pattern; and a conductor block supporting the lower surface of the dielectric substrate. The lower electrode of the bypass capacitor having an overlap area overlapping with the upper surface of the dielectric substrate, the lower electrode of the bypass capacitor having an overhang area overhanging from the upper surface of the dielectric substrate.

A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.