An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.

A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.

A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Transistor devices are provided. In some example implementations, a magnetic field sensor chip is fitted on a load electrode of a transistor chip. In other example implementations, two magnetic field sensors are arranged on a load electrode of a transistor chip in such a way that they measure different effective magnetic fields in the event of current flow through the transistor chip.

An electronic module has a first substrate 11, a first electronic element 13 provided on one side of the first substrate 11, a first connection body 60 provided on one side of the first electronic element 13, a second electronic element 23 provided on one side of the first connection body 60, a second substrate 21 provided on one side of the second electronic element 23, and an abutment body 250 that abuts on a face on one side of the second electronic element 23 and is capable of imparting a force toward one side with respect to the second substrate 21.

An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die. The first conductive clip-die bonding layer bonds the first clip bond horizontal planar portion to the first die contact pad, and the spacers maintain a uniform Bond Line Thickness (BLT) of the first conductive clip-die bonding layer.

A low-cost semiconductor package using a conductive metal structure includes a lead frame including a pad and a lead, a semiconductor chip attached onto the pad of the lead frame, an Aluminum (Al) pad formed on the semiconductor chip, a clip structure having one side adhered to the Al pad and the other side adhered to the lead of the lead frame, and a sealing member formed to surround the semiconductor chip and the clip structure via molding, wherein the semiconductor chip is adhered directly to a junction of the lead frame through a first adhesive layer formed of a solder or epoxy resin-based material and is adhered directly to a junction of the Al pad and the clip structure through a second adhesive layer formed of a solder-based material.

A semiconductor module includes a laminated substrate that includes a heat radiating plate, and an insulation layer having a conductive pattern thereof and being disposed on a top surface of the heat radiating plate, a semiconductor element disposed on a top surface of the conductive pattern, an integrated circuit that controls driving of the semiconductor element, a control-side lead frame having a primary surface on which the integrated circuit is disposed, and a mold resin that seals the laminated substrate, the semiconductor element, the integrated circuit, and the control-side lead frame. The control-side lead frame has a rod-shaped first pin having a first end, a first end side of the first pin extending toward the top surface of the heat radiating plate, and the heat radiating plate has at least one insertion hole into one of which the first end of the first pin is press-fitted.

Provided is a semiconductor package including: at least one first substrate including at least one first substrate terminal extended therefrom; at least one second substrate joined to the upper surface of the first substrate using ultrasonic welding; at least one semiconductor chip joined to the upper surface of the second substrate; a package housing covering the at least one semiconductor chip and an area of the second substrate, where ultrasonic welding is performed; and terminals separated from the first substrate, electrically connected to the at least one semiconductor chip through electric signals, and at least one of them is exposed to the outside of the package housing, wherein a thickness of the terminals formed inside the package housing is same as or smaller than a thickness of the first substrate and the second substrate includes at least one embossing groove on the upper surface thereof.