Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high-humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part.

A semiconductor package assembly includes a carrier with a die attach surface and a contact pad separated from the die attach surface, a semiconductor die mounted on the die attach surface, the semiconductor die having a front side metallization that faces away from the die attach surface, an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad, and an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon. The interconnect ribbon includes a layer stack of a first metal layer and a second layer formed on top of the first metal layer. The first metal layer includes a different metal as the second metal layer. The first metal layer faces the front side metallization.

A semiconductor package assembly includes a carrier with a die attach surface and a contact pad separated from the die attach surface, a semiconductor die mounted on the die attach surface, the semiconductor die having a front side metallization that faces away from the die attach surface, an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad, and an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon. The interconnect ribbon includes a layer stack of a first metal layer and a second layer formed on top of the first metal layer. The first metal layer includes a different metal as the second metal layer. The first metal layer faces the front side metallization.

A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.

A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.