A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.

A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.

A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.

A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.

In a described example, an apparatus includes: a package substrate including a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead and a third lead; and a semiconductor die including a temperature sensor mounted on the die pad. The semiconductor die includes a first metallization layer being a metallization layer closest to the active surface of the semiconductor die, and successive metallization layers overlying the previous metallization layer, the metallization layers including a respective conductor layer in a dielectric material for the particular metallization layer and conductive vias; and the temperature sensor formed of the conductor layer in an uppermost metallization layer and coupled to the second lead and to the third lead. The semiconductor die includes a high voltage ring formed in the uppermost metallization layer, spaced from and surrounding the temperature sensor.

In a described example, an apparatus includes: a package substrate including a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead and a third lead; and a semiconductor die including a temperature sensor mounted on the die pad. The semiconductor die includes a first metallization layer being a metallization layer closest to the active surface of the semiconductor die, and successive metallization layers overlying the previous metallization layer, the metallization layers including a respective conductor layer in a dielectric material for the particular metallization layer and conductive vias; and the temperature sensor formed of the conductor layer in an uppermost metallization layer and coupled to the second lead and to the third lead. The semiconductor die includes a high voltage ring formed in the uppermost metallization layer, spaced from and surrounding the temperature sensor.

A semiconductor package includes: a base substrate; a semiconductor chip stack including a plurality of semiconductor chips stacked on the base substrate in a first direction and each having an upper surface on which a plurality of pads are disposed; and bonding wire structures electrically connecting the base substrate and the semiconductor chips. The semiconductor chip stack includes a lower semiconductor chip stack and an upper semiconductor chip stack on the lower semiconductor chip stack. The plurality of semiconductor chips include a first semiconductor chip at an uppermost portion of the lower semiconductor chip stack and second semiconductor chips. The plurality of pads include first pads, aligned in a second direction, and second pads, spaced apart from the first pads in a third direction. The first pad on the first semiconductor chip, has an area larger than an area of each of the first pads on the second semiconductor chips.

A semiconductor package includes: a base substrate; a semiconductor chip stack including a plurality of semiconductor chips stacked on the base substrate in a first direction and each having an upper surface on which a plurality of pads are disposed; and bonding wire structures electrically connecting the base substrate and the semiconductor chips. The semiconductor chip stack includes a lower semiconductor chip stack and an upper semiconductor chip stack on the lower semiconductor chip stack. The plurality of semiconductor chips include a first semiconductor chip at an uppermost portion of the lower semiconductor chip stack and second semiconductor chips. The plurality of pads include first pads, aligned in a second direction, and second pads, spaced apart from the first pads in a third direction. The first pad on the first semiconductor chip, has an area larger than an area of each of the first pads on the second semiconductor chips.

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.