A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.

A semiconductor device of embodiments includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer connected to the first main terminal, a second metal layer connected to the second main terminal, a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal, a first semiconductor chip and a second semiconductor chip provided on the first metal layer, a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer, and a conductive member on the second metal layer. Then, the second metal layer includes a slit. The conductive member is provided between the end portion of the second metal layer and the slit.

A semiconductor device of embodiments includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer connected to the first main terminal, a second metal layer connected to the second main terminal, a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal, a first semiconductor chip and a second semiconductor chip provided on the first metal layer, a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer, and a conductive member on the second metal layer. Then, the second metal layer includes a slit. The conductive member is provided between the end portion of the second metal layer and the slit.

There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (μm/μm.sup.2) or more and 1.6 (μm/μm.sup.2) or less.

There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (μm/μm.sup.2) or more and 1.6 (μm/μm.sup.2) or less.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.

An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.