A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

A semiconductor apparatus of the present disclosure includes: a first semiconductor component in which a first circuit unit is provided; and a second semiconductor component in which a second circuit unit is provided and which is stacked to the first semiconductor component, and the second semiconductor component includes a capacitor unit as a decoupling capacitor having a first node and a second node that are connected to the first circuit unit.

A semiconductor apparatus of the present disclosure includes: a first semiconductor component in which a first circuit unit is provided; and a second semiconductor component in which a second circuit unit is provided and which is stacked to the first semiconductor component, and the second semiconductor component includes a capacitor unit as a decoupling capacitor having a first node and a second node that are connected to the first circuit unit.

A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality of stubs respectively on a plurality of pads arranged in the peripheral area, and a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate while exposing an upper surface of at least one of the plurality of stubs to outside of the molding unit, wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat.

A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality of stubs respectively on a plurality of pads arranged in the peripheral area, and a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate while exposing an upper surface of at least one of the plurality of stubs to outside of the molding unit, wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.

A semiconductor package includes: semiconductor chips being offset-stacked to expose edge regions adjacent to first side surfaces; chip pads disposed in each of the edge regions of the semiconductor chips, the chip pads including a plurality of first chip pads arranged in a first column and a plurality of second chip pads arranged in a second column; a horizontal common interconnector having one end connected to the second chip pad of a semiconductor chip of the semiconductor chips, and another end connected to the first chip pad of another semiconductor chip; and a vertical common interconnector having one end connected to the second chip pad of the uppermost semiconductor chip, which is electrically connected to the first chip pad of the uppermost semiconductor chip connected to the horizontal common interconnector.