The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.

The present disclosure provides a semiconductor packaging method and a semiconductor package device. The method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface; soldering pads disposed at the front surface of a chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate. A first end of the metal part away from a corresponding soldering pad is in coplanar with the transparent protective layer; and the first end of the metal part is not covered by the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part to electrically connect the chip with the circuit board.

The present disclosure provides a semiconductor packaging method and a semiconductor package device. The method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface; soldering pads disposed at the front surface of a chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate. A first end of the metal part away from a corresponding soldering pad is in coplanar with the transparent protective layer; and the first end of the metal part is not covered by the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part to electrically connect the chip with the circuit board.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Semiconductor chip package array is provided. The semiconductor chip package array includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, a plurality of support units arranged in a matrix, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves are connected to adjacent support units of the plurality of support units. The chips are disposed on and electrically connected to the plurality of support units. An encapsulating material encapsulates the chips and at least a portion of the plurality of support units, and fill the first grooves to form the encapsulating layer. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Semiconductor chip package array is provided. The semiconductor chip package array includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, a plurality of support units arranged in a matrix, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves are connected to adjacent support units of the plurality of support units. The chips are disposed on and electrically connected to the plurality of support units. An encapsulating material encapsulates the chips and at least a portion of the plurality of support units, and fill the first grooves to form the encapsulating layer. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

The present invention discloses a high-reliability copper alloy bonding wire for electronic packaging and a preparation method therefor; the bonding wire comprises the following raw material components in percentage by weight: a copper content being 99.75%-99.96%, a tungsten content being 0.01-0.1%, a silver content being 0.01%-0.03%, a scandium content being 0.01%-0.02%, a titanium content being 0.001%-0.03%, a chromium content being 0.001%-0.03%, and an iron content being 0.001%-0.02%. The preparation method therefor comprises: extracting high-purity copper with a purity greater than 99.99%, preparing same as copper alloy ingots, and further preparing same as as-cast copper alloy crude bars, drawing the crude bars to form copper alloy wires, subjecting same to a heat treatment, and then precise drawing, a heat treatment, and cleaning to obtain copper alloy bonding wires of different specifications.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.

Semiconductor packages and modules are provided. The semiconductor package includes a package substrate; a semiconductor chip disposed on the package substrate; a molding layer covering the semiconductor chip and a first region of the package substrate; and a functional layer covering the molding layer and extending onto a second region of the package substrate that surrounds the first region.