In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.