There is provided a novel Cu bonding wire that achieves a favorable FAB shape and reduces a galvanic corrosion in a high-temperature environment to achieve a favorable bond reliability of the 2nd bonding part. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, and the total number of measurement points in the coating layer whose absolute deviation from the average value X is 0.3× or less is 50% or more relative to the total number of measurement points in the coating layer.

A semiconductor device includes: a substrate; a device region provided in the substrate; a terminal covering the device region in a plan view; a plurality of pseudo-bumps densely arranged on the terminal in a state of being opened from a wire; and at least one genuine bump arranged more sparsely than the plurality of the pseudo-bumps on the terminal in a state of being connected to the wire.

There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieve a favorable bond reliability of the 2nd bonding part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, the total number of measurement points in the coating layer whose absolute deviation from the average value X is or less is 50% or more relative to the total number of measurement points in the coating layer, and the bonding wire satisfies at least one of following conditions (i) and (ii): (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less; and (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads. The gull-wing leads are formed on the intermediate pads.

A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads. The gull-wing leads are formed on the intermediate pads.

A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

Compliant interconnect based on deformable wires compressed against contacts on chip scale packages (CSP). Including deformable rubbery overcoat on at least one of the CSP. The use of substantially optically transmitting overcoat means to secure the assembly is also disclosed. The use of various wires including but not limited to gold, silver, aluminum, carbon nanotube yarns, and composite wires also disclosed.

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.