A substrate for a SIP is that has a portion of its top surface covered with spaced apart electrically conductive landing pads for electrical connection to components located on the surface and the landing pads serve as interconnection pads for making electrical connections between at least a portion of said pads when interconnected by a segment of bond wire to form at least a portion of the SIP. Methods for use of the universal substrate in SIP system design and manufacture of a SIP.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

A siliconized heterogeneous optical engine. In some embodiments, the siliconized heterogeneous optical engine includes a photonic integrated circuit; an electro-optical chip, on a top surface of the photonic integrated circuit; an electronic integrated circuit, on the top surface of the photonic integrated circuit; an interposer, on the top surface of the photonic integrated circuit; a redistribution layer, on a top surface of the interposer, the redistribution layer including a plurality of conductive traces; and a plurality of protruding conductors, on the conductive traces of the redistribution layer. The electronic integrated circuit may be electrically connected to the electro-optical chip and to a conductive trace of the plurality of conductive traces of the redistribution layer.

An integrated circuit package includes a transmission line structure, wire bonds, a first post and a second post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line between two ground lines and sealed from exposure to air. The wire bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The wire bonds are selected to have an impedance matched to impedance of the integrated circuit. The first post supports the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The second post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the wire bonds.

A display substrate, including: a base substrate including at least a side edge and a display area; a plurality of pixel units disposed in the display area, a second pixel unit is located on a side of a first pixel unit close to the side edge, edges of the second pixel unit include the side edge, a third pixel unit is located between the first pixel unit and the second pixel unit, and the third pixel unit is adjacent to the second pixel unit; and a plurality of light emitting diode chips disposed on the base substrate a first light emitting diode chip is located in the first pixel unit, a part of a second light emitting diode chip is located in the second pixel unit, and the other part of the second light emitting diode chip is located in the third pixel unit.

A semiconductor device according to one embodiment includes: a semiconductor chip having a transistor and a drain pad provided on a board; a capacitor having an upper electrode and a lower electrode interposing a dielectric; a pad; and an empty pad provided on the board of the semiconductor chip. The semiconductor device further includes: a first wire connecting the pad and the drain pad of the semiconductor chip to each other; a second wire connecting the empty pad and the upper electrode of the capacitor to each other; and a third wire connecting the pad and the empty pad to each other.

A display device includes a substrate, a plurality of pixel electrodes on the substrate and spaced apart from each other, a plurality of light-emitting elements on the plurality of pixel electrodes, respectively, and a common electrode layer on the plurality of light-emitting elements and to which a common voltage is applied. The plurality of light-emitting elements include a first light-emitting element that is configured to emit first light according to a first driving current and a second light-emitting element that is configured to emit second light according to a second driving current. An active layer of the first light-emitting element is the same as an active layer of the second light-emitting element.