An imaging catheter assembly is provided. The imaging catheter assembly includes an interposer including a multi-layered substrate structure, wherein the multi-layered substrate structure includes a first plurality of conductive contact pads coupled to a second plurality of conductive contact pads via a plurality of conductive lines; an imaging component coupled to the interposer via the first plurality of conductive contact pads; and an electrical cable coupled to the interposer via the second plurality of conductive contact pads and in communication with the imaging component.

A lighting device and a method of manufacturing a lighting device are described. A lighting device includes a heat sink providing a first mounting area for at least one LED element, a second mounting area for at least one electrical connection assembly, and a cavity adjacent the first mounting area. An inner part is arranged at least partially inside the cavity and includes at least a first and a second connection terminal and at least one electrical connection path. The first and the second connection terminal are provided on a surface of the inner part. The first connection terminal is arranged between the first mounting area and the second connection terminal. The second connection terminal is arranged between the second mounting area and the first connection terminal. The electrical connection path is provided at least partially inside the inner part connecting the first and second electrical terminal.

A semiconductor device (4a-4d) and a wiring device (5) are provided on a main surface of a base plate (1). A first wire (11a-11e) connects an external electrode (7a-7e) and a first relay pad (8a-8e) of the wiring device (5). A second wire (12a-12e) connects a pad (13a-13e) of the semiconductor device (4a-4d) and the second relay pad (9a-9e) of the wiring device (5). Resin (15) seals the semiconductor device (4a-4d), the wiring device (5) and the first and second wires (11a-11e,12a-12e). The second wire (12a-12e) is thinner than the first wire (11a-11e). The pad (13a-13e) is smaller than the first relay pad (8a-8e).

The semiconductor device includes an insulating circuit substrate mounted with a semiconductor element; an external terminal; a base including a support portion; an adhesive sheet; and a sealing portion covering the semiconductor element. The support portion has a first surface, a second surface on the side opposite to the first surface, and a first opening opened at the first surface and the second surface. The insulating circuit substrate is disposed in the first opening. The adhesive sheet is disposed on the second surface of the support portion and has a second opening in which the semiconductor element is disposed in plan view. The adhesive sheet is projected into the first opening in plan view and adhered to a circuit block. The external terminal is adhered on the adhesive sheet and has a connecting surface to which a bonding wire is connected.

A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.

According to one embodiment, a high-frequency amplifier includes an active element and an output matching circuit. The active element is provided on a substrate. The active element is configured to amplify a signal having a frequency band. The active element includes a cell region. The output matching circuit is connected to the active element. The output matching circuit includes a wire, a transmission line and an output terminal. The wire includes an input end and an output end. The input end of the wire is connected to an output part of the cell region of the active element. The transmission line is provided on the substrate. The transmission line includes an input part and an output part. The input part of the transmission line is connected to the output end of the wire. The output terminal is provided on the substrate.

One aspect of the invention relates to an electronic module comprising a module housing and an electrically conductive connection element. The connection element has a first portion and a second portion, and also a shaft between the first portion and the second portion. The connection element, which is provided with a non-metallic coating in the region of the shaft, is injected together with the coating in the region of the shaft into the module housing, such that the connection element is fixed in the module housing.

A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.

An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.