H01L2224/48177

SEMICONDUCTOR MODULE

A semiconductor module includes a semiconductor switching element, a multiple of bases, on at least one of which the semiconductor switching element is mounted, a molded resin that seals the semiconductor switching element and the multiple of bases, a multiple of terminals formed integrally with each one of the multiple of bases and provided extending from an outer periphery side face of the molded resin, and a recessed portion or a protruding portion having a depth or a height such that creepage distance between the multiple of terminals is secured, and formed so as to cross an interval between the multiple of terminals, in one portion of the outer periphery side face of the molded resin between the multiple of terminals.

PACKAGE WITH SELECTIVE CORROSION PROTECTION OF ELECTRIC CONNECTION STRUCTURE
20210028125 · 2021-01-28 · ·

A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant encapsulating at least part of the electronic component and only part of the carrier so that another exposed part of the carrier is exposed with regard to the encapsulant. The exposed part of the carrier comprises an electric connection structure and a corrosion protection structure. One of the electric connection structure and the corrosion protection structure is selectively formed on only a sub-portion of the other one of the electric connection structure and the corrosion protection structure outside of the encapsulant.

LEAD FRAMES INCLUDING LEAD POSTS IN DIFFERENT PLANES

A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

Integrated white light source using a laser diode and a phosphor in a surface mount device package

The embodiments described herein provide a device and method for an integrated white colored electromagnetic radiation source using a combination of laser diode excitation sources based on gallium and nitrogen containing materials and light emitting source based on phosphor materials. A violet, blue, or other wavelength laser diode source based on gallium and nitrogen materials may be closely integrated with phosphor materials, such as yellow phosphors, to form a compact, high-brightness, and highly-efficient, white light source. The phosphor material is provided with a plurality of scattering centers scribed on an excitation surface or inside bulk of a plate to scatter electromagnetic radiation of a laser beam from the excitation source incident on the excitation surface to enhance generation and quality of an emitted light from the phosphor material for outputting a white light emission either in reflection mode or transmission mode.

GROUNDING LIDS IN INTEGRATED CIRCUIT DEVICES

A semiconductor device includes a substrate, an IC die mounted on the substrate, packaging encapsulant on the substrate, a cavity in the packaging encapsulant, a conductive lid attached to the packaging encapsulant over the IC die, an electrical ground path in the substrate, and a first conductive structure in the cavity. The first conductive structure includes a first end electrically coupled to the conductive lid and a second end electrically coupled to the electrical ground path.

METHOD FOR TESTING A HIGH VOLTAGE TRANSISTOR WITH A FIELD PLATE
20200403071 · 2020-12-24 ·

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

QFN pin routing thru lead frame etching

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

APPARATUSES AND METHODS FOR COUPLING A WAVEGUIDE STRUCTURE TO AN INTEGRATED CIRCUIT PACKAGE

Aspects are directed to a waveguide structure that can couple to an integrated circuit package. The IC package includes a plurality of pillars to provide a path for carrying millimeter-wave signals, each of the pillars having a first end portion to connect to the IC package and a second end portion to connect to a waveguide antenna. Also, as may be optionally included, waveguide shields provide electro-magnetic isolation for the pillars and a micro-strip connector to provide connection between the second end portions (of the pillars) and to the waveguide antenna. Further included in the apparatus are a plurality of bond wires to connect the IC package and a lead frame, and to carry signals form circuitry of the IC package to the printed circuit board on which the package is mounted for transmission of radar signals via the waveguide antenna.

Power amplifier modules including transistor with grading and semiconductor resistor

One aspect of this disclosure is a power amplifier module that includes a power amplifier on a substrate and a semiconductor resistor on the substrate. The power amplifier includes a bipolar transistor having a collector, a base, and an emitter. The collector has a doping concentration of at least 310.sup.16 cm.sup.3 at an interface with the base. The collector also has at least a first grading in which doping concentration increases away from the base. The semiconductor resistor includes a resistive layer that that includes the same material as a layer of the bipolar transistor. Other embodiments of the module are provided along with related methods and components thereof.

Chip packaging structure and method, and electronic device

A chip packaging structure and method, and an electronic device, are provided. The chip packaging structure includes a support, a chip, at least one conductor, and a package for plastic packaging the support, the chip and the conductor. The chip is arranged on an upper surface of the support, a chip pad is formed on the upper surface of the chip, and the chip pad is connected to an external pad of the support by a bonding wire. The conductor is connected to the external pad or a ground pad of the chip pad, and the shortest distance from the conductor to the upper surface of the package is less than the shortest distance from the bonding wire to the upper surface of the package, whereby chip failure caused by static electricity discharge is greatly reduced.