A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.

An imaging system using ultraviolet light or a manufacturing apparatus including the imaging system is provided. An imaging system includes an imaging element and a light source, which operates the imaging element with light that is emitted from the light source and reflected or transmitted by an object. A pixel included in the imaging element includes a photoelectric conversion element and a charge holding part. The light source has a function of emitting ultraviolet light to an object. The photoelectric conversion element is irradiated with the ultraviolet light reflected or transmitted by the object. The photoelectric conversion element has a function of changing the potential of the charge holding part when irradiated with the ultraviolet light and retaining the potential when not irradiated with the ultraviolet light.

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned into a first portion of a first passive circuit element. The first conductive layer is patterned to include a first coiled portion. A second conductive layer is formed over a second surface of the substrate. The second conductive layer is patterned into a second portion of the first passive circuit element. The second conductive layer is patterned to include a second coiled portion exhibiting mutual inductance with the first coiled portion. A conductive via formed through the substrate is coupled between the first conductive layer and second conductive layer. A semiconductor component is disposed over the substrate and electrically coupled to the first passive circuit element. An encapsulant is deposited over the semiconductor component and substrate. The substrate is mounted to a printed circuit board.

A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50.

An electronic element mounting substrate includes a first insulating layer, a second insulating layer, a first metal layer, and a through-hole conductor. The first insulating layer and the second insulating layer are aligned in a first direction. The first metal layer is positioned between the first insulating layer and the second insulating layer. The through-hole conductor extends in the first direction from the first insulating layer through the second insulating layer. The first metal layer includes a first portion positioned away from the through-hole conductor and a second portion in contact with the through-hole conductor. The second portion has a larger thickness than the first portion.

An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.