A semiconductor device and a method of making the same. The device includes a substrate mounted on a carrier, the substrate comprising a High Electron Mobility Transistor (HEMT) having a source, a gate and a drain. The carrier comprises an electrically conductive shielding portion for providing shielding against electromagnetic interference associated with switching of the device during operation. The electrically conductive shielding portion is electrically isolated from the source and from the backside of the substrate.

A ceramic substrate is provided, including: a board having a first surface and a second surface opposing the first surface; first electrical contact pads disposed on the first surface; second electrical contact pads disposed on the second surface; conductive pillars disposed in the board and connecting the first surface and the second surface to electrically connect the electrical contact pad and the second electrical contact pad; a first heat conductive pad disposed on the first surface; a second heat conductive pad disposed on the second surface; and a heat conductive pillar disposed in the board and connecting the first surface and the second surface to contact and be coupled with the first heat conductive pad and the second heat conductive pad, wherein the heat conductive pillar has a width greater than or equal to widths of the conductive pillars and greater than or equal to 300 micrometers.

In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.

The invention relates to a method for manufacturing a power electronic module (1) by additive manufacturing, characterized in that it comprises the steps of: making or fixing preforms (15) of polymer material on at least one face of an insulating substrate (2a) covered with at least one layer of metal (2b, 2c), referred to as a metallized substrate (2), depositing a first metal layer (17) on the preform (15), depositing by electroforming a second metal layer (18) on the first metal layer (17).

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

A method for producing a semiconductor module, involving the steps: providing a carrier plate and a substrate having a bonding layer arranged on a surface of the carrier plate or the substrate, applying adhesive in multiple adhesive areas of the carrier plate or the substrate which are free from the bonding layer, positioning the substrate on the carrier plate such that the substrate and the carrier plate are in contact with the bonding layer and the adhesive, and joining the substrate and the carrier plate across the bonding layer by melting or sintering of the bonding layer.