Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier.

A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier.

A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the control circuit; first conductive coupling members configured to electrically couple bonding pads of the nonvolatile memory chip to the redistribution structures; second conductive coupling members configured to electrically couple the redistribution structures to the first pads; and third conductive coupling members configured to electrically couple the second pads to the substrate.

A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the control circuit; first conductive coupling members configured to electrically couple bonding pads of the nonvolatile memory chip to the redistribution structures; second conductive coupling members configured to electrically couple the redistribution structures to the first pads; and third conductive coupling members configured to electrically couple the second pads to the substrate.

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.