In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.

A method of equalization for high-speed processing and an equalizer thereof are proposed. The method of equalization includes determining a filter coefficient applied to a transmitter equalizer provided with a 2-tap precoder according to an approximate channel response characteristic, generating a pre-equalization signal by removing precursor ISI of a transmission feedback signal by the precoder to which the filter coefficient is applied, so as to output the pre-equalization signal as a transmitting signal, and receiving a transmission signal and generating an equalization signal by removing postcursor ISI of the received transmission signal by a receiver equalizer provided with a feedback filter having auxiliary coefficients for compensating for a difference between an overall channel response of the transmission signal and a channel response based on the precoder.

Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.

Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.

Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.

Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.

Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.

Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.