A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

The present invention provides a method for fabricating a semiconductor device capable of improving the contact resistance. According to an embodiment of the present invention, the method for fabricating the semiconductor device comprises: forming a doped region by doping and activation annealing a first dopant on a substrate; forming an interlayer insulating layer on the substrate; forming a contact hole exposing the doped region by etching the interlayer insulating layer; exposing the doped region to a pre-annealing; forming an additional doped region by doping a second dopant on a pre-annealed doped region; exposing the additional doped region to a post-annealing; and forming metal silicide on the additional doped region.

A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.

An isolator includes a first insulating portion, a first electrode provided in the first insulating portion, a second insulating portion provided on the first insulating portion and the first electrode, a third insulating portion provided on the second insulating portion, and a second electrode provided in the third insulating portion. The second insulating portion includes a plurality of first voids and a second void. The plurality of first voids are arranged in a first direction parallel to an interface between the first insulating portion and the second insulating portion. At least one of the first voids is provided under the second void.

The present disclosure a method for manufacturing a metal-oxide-semiconductor (MOS) transistor device. The method. includes steps of providing a substrate; forming a gate electrode over the substrate; forming a source region and a drain region in the substrate; depositing an isolating layer over the substrate and the gate electrode; forming a plurality of contact holes in the isolating layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; depositing a contact liner in the contact holes; and depositing a conductive material in the contact holes, wherein the conductive material is surrounded by the contact liner.

A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.