The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.

Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

A fabrication method for a semiconductor structure is provided. The method includes: forming a base substrate; forming gate structures on the base substrate where each gate structure includes a first gate portion with first doping ions on the base substrate and a second gate portion on the first gate portion; forming a metal layer on the second gate portions; and forming a metal silicide layer by reacting a portion of the metal layer with each second gate portion through an annealing process. When forming the metal silicide layers, a reaction between the metal layer and the second gate portions has a first reacting rate and a reaction between the metal layer and the first gate portions has a second reacting rate; and the second reacting rate is smaller than the first reacting rate.

A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).