An indirect heating method using a laser according to an aspect of the present disclosure includes: a first process of adjacently placing a first material structure containing a metal and a second material structure containing a mineral; and a second process of directly heating the first material structure to indirectly heat the second material structure adjacent to the first material structure by emitting a laser to the first material structure.

In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Methods for depositing a metal silicide are provide and include heating a substrate having a silicon-containing surface to a deposition temperature, and exposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process. The deposition gas contains a silicon precursor, a titanium or other metal precursor, and a phosphorus or other non-metal precursor.

A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

A cryogenic semiconductor device includes isolation regions defining an active region having a first P-type ion concentration in a substrate, a gate structure in the substrate, and an ion implantation region having a second P-type ion concentration in the active region below the gate structure, wherein the gate structure includes a gate dielectric layer conformally disposed on inner sidewalls of a gate trench, a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.

A semiconductor device includes a substrate having a first area and a second area and an active area limited by an isolation layer in the first area and the second area, a p-type gate electrode doped with p-type impurities and including a p-type lower gate layer and a p-type upper gate layer on the p-type lower gate layer with a first gate dielectric layer disposed between the active area and the p-type gate electrode in the first area, and an n-type gate electrode doped with n-type impurities and including an n-type lower gate layer and an n-type upper gate layer on the n-type lower gate layer with a second gate dielectric layer disposed between the active area and the n-type gate electrode in the second area.

Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method for fabricating semiconductor device may include forming a trench in a substrate; forming a gate dielectric layer over the trench, embedding a first dipole inducing portion in the gate dielectric layer on a lower side of the trench, filling a lower gate over the first dipole inducing portion, embedding a second dipole inducing portion in the gate dielectric layer on an upper side of the trench and forming an upper gate over the lower gate.

A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.

A method of manufacturing a semiconductor device includes: forming a trench in an insulating interlayer by etching the insulating interlayer; forming a conductive layer on bottom, side, and upper surfaces of the insulating interlayer where the trench is formed, using a first deposition process, the conductive layer on the bottom surface of the trench being thicker than the conductive layer on the side surface of the trench; forming a sacrificial layer in the trench covering the conductive layer formed on the bottom surface of the trench using a second deposition process different from the first deposition process; selectively removing the conductive layer formed on the upper surface of the insulating interlayer and formed on the side surface of the trench left exposed through the sacrificial layer; and selectively removing the sacrificial layer, to form a conductive line using the conductive layer remaining on the bottom surface of the trench.

A semiconductor device includes a substrate, a gate insulating layer on the substrate, and a stacked semiconductor layer. The stacked semiconductor layer includes a first layer formed on the gate insulating layer and including a phosphorus-doped polycrystalline semiconductor, a second layer formed on the first layer and including a carbon-doped polycrystalline semiconductor, and a third layer formed on the second layer and including a phosphorus-doped or undoped polycrystalline semiconductor. The semiconductor device further includes a metal layer on or above the stacked semiconductor layer. The third layer includes less phosphorus than the first layer or does not include phosphorus.