Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.

The present invention is a composition for forming a metal oxide film, including: (A) a metal oxide nanoparticle; (B) a flowability accelerator containing a resin having a structural unit represented by the following general formula (1); (C) a dispersion stabilizer having two or more benzene rings or having one benzene ring and a structure represented by the following general formula (C-1), and the dispersion stabilizer being composed of an aromatic group-containing compound having a molecular weight of 500 or less; and (D) an organic solvent, wherein the flowability accelerator (B) has a content of 9 mass % or more in an entirety of the composition, a ratio Mw/Mn of 2.50?Mw/Mn?9.00, and the flowability accelerator (B) having no cardo structure. Thus, there can be provided a composition for forming a metal oxide film that has excellent dry etching resistance compared with a conventional organic underlayer film material, that has excellent filling property compared with a conventional metal hard mask, that can reduce cracking with forming a thick film, and that has excellent storage stability;

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A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

Pattern-multiplication via a multiple step ion beam etching process utilizing multiple etching steps. The ion beam is stationary, unidirectional or non-rotational in relation to the surface being etched during the etching steps, but sequential etching steps can utilize an opposite etching direction. Masking elements are used to create additional masking elements, resulting in decreased spacing between adjacent structures and increased structure density.

Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer etch and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma to modify a surface of the substrate and exposing the modified surface to a second plasma at a bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate using a precursor having a chemical formula of C.sub.xH.sub.y, where x and y are integers greater than or equal to 1. ALE and selective deposition may be performed without breaking vacuum.

A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.