An integrated circuit device includes a substrate, a first isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The first isolation feature is in the transition region. The substrate includes a protrusion portion between a first portion and a second portion of the first isolation feature, the second portion is between the first portion and the cell region, and a top surface of the first portion of the first isolation feature has a first part and a second part lower than the first part, and the second part is between the first part and the second portion of the first isolation feature. The memory cell is over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.

A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.

Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.

The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent. The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.

Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. The methods include forming a stack structure in a staircase region and a core array region, the stack structure including a staircase structure in the staircase region; forming a dielectric layer over the staircase region and a peripheral region outside the stack structure; and polishing the dielectric layer using an auto-stop slurry containing a ceria-based abrasive.

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.