Patent classifications
H01L21/31056
Semiconductor device having deep trench structure and method of manufacturing thereof
A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
Semiconductor device and manufacturing method thereof
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
APPARATUS FOR AND METHOD OF POLISHING SURFACE OF SUBSTRATE
According to one or more embodiments, there is provided an apparatus for polishing a surface of a substrate to remove a resin layer formed on the surface of the substrate having a groove, the apparatus including: a laser irradiation apparatus configured to irradiate a laser to the resin layer to remove at least a portion of a resin from the resin layer except for a portion of the resin layer arranged in the groove.
Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
COMPOSITION FOR ETCHING AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.
COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.
COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.
COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.
COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.
COMPOSITION FOR ETCHING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.