A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

A method includes forming an inner chamber in a process chamber of a plasma processing apparatus, the inner chamber having smaller volume than the process chamber. At least one gas is introduced into the inner chamber, and flow of the at least one gas into the inner chamber is measured. The flow of the at least one gas is adjusted to a desired rate, and a wafer is processed by the at least one gas at the desired rate while the inner chamber is not formed.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor device etching equipment. The semiconductor structure manufacturing method includes: providing a semiconductor structure to be processed, putting the semiconductor structure to be processed in a processing chamber, wherein the semiconductor structure to be processed includes a substrate and target structures to be processed located on the substrate, and sidewalls of the target structures to be processed are covered with bromine-containing polymer layers; removing the bromine-containing polymer layers, and forming a semiconductor structure; and removing products resulting from a process of removing the bromine-containing polymer layers from the processing chamber.

The present application provides a semiconductor structure fabrication method, a semiconductor structure and a memory. The semiconductor structure fabrication method includes: providing a substrate, the substrate including a first surface and a second surface opposite to each other; forming a first dielectric layer on the first surface of the substrate, wherein semiconductor devices are formed in the first dielectric layer; forming first trenches extending into the substrate in the first dielectric layer; forming a first barrier layer on the first dielectric layer, the first barrier layer covering inner walls of the first trenches and a surface of the first dielectric layer; forming second trenches corresponding to the first trenches on the second surface of the substrate; and forming a second barrier layer on the substrate, the second barrier layer covering the second surface and inner walls of the second trenches.

A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

A method of patterning a substrate. The method may include providing a cavity in a layer, disposed on the substrate, the cavity having a first length along a first direction and a first width along a second direction, perpendicular to the first direction, and wherein the layer has a first height along a third direction, perpendicular to the first direction and the second direction. The method may include depositing a sacrificial layer over the cavity in a first deposition procedure; and directing angled ions to the cavity in a first exposure, wherein the cavity is etched, and wherein after the first exposure, the cavity has a second length along the first direction, greater than the first length, and wherein the cavity has a second width along the second direction, no greater than the first width.

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.