H01L21/31116

POWER CONTROL FOR RF IMPEDANCE MATCHING NETWORK
20230215696 · 2023-07-06 ·

In one embodiment, a system includes an RF source and an RF impedance matching circuit receiving RF power from the RF source. The matching circuit includes at least one variable reactance element, a sensor operably coupled to a component of the matching circuit, and a control circuit. The control circuit receives a signal from the sensor indicative of a parameter value. Upon determining the parameter value meets a first predetermined condition, the control circuit transmits a control signal to the RF source causing the RF source to carry out a power control scheme. The power control scheme causes the RF source to reduce or maintain the RF power without turning off the RF power.

Substrate processing device
11551949 · 2023-01-10 · ·

According to one embodiment, a substrate processing device includes a stage configured to mount a substrate, a mold having a first surface facing an upper surface of an outer peripheral edge of the substrate and a second surface facing a side surface of an outer peripheral continuous with the upper surface of the outer peripheral edge, a mold moving mechanism configured to move the mold to bring the first surface close to the upper surface of the outer peripheral edge of the substrate and the second surface close to the side surface of the outer peripheral of the substrate, and a nozzle arranged in the mold, wherein the nozzle ejects resist.

METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES USING CARBONYL COMPOUNDS

To manufacture an integrated circuit (IC) device, a structure in which a first material film including silicon atoms and nitrogen atoms and a second material film devoid of nitrogen atoms is formed on a substrate. A carbonyl compound having a functional group without an α-hydrogen is applied to the structure, and thus, an inhibitor is selectively formed only on an exposed surface of the first material film from among the first material film and the second material film.

ELECTRODE TUNING, DEPOSITING, AND ETCHING METHODS
20230215735 · 2023-07-06 ·

A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.

FinFETs with low source/drain contact resistance

An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

Semiconductor device and method for manufacturing the same

According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

Transistor contacts and methods of forming the same

In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

MANUFACTURING METHOD OF MEMORY DEVICE USING MASK PATTERNS
20230005754 · 2023-01-05 · ·

There is a method of manufacturing a memory device. The method includes forming a mask layer on an etching target layer; forming, on the mask layer, a compensation layer with a second impurity that chemically bonds to the mask layer with a first impurity; performing a first etching process that patterns the compensation layer and the mask layer to form a mask pattern; and performing a second etching process that etches the etching target layer, which is exposed through openings of the mask pattern.

ETCHING METHOD AND PLASMA PROCESSING APPARATUS

An etching method includes: (a) providing a substrate including a first region containing silicon and nitrogen and a second region containing silicon and oxygen; (b) forming a tungsten-containing deposit on the first region using a first plasma generated from a first processing gas containing fluorine, tungsten, and at least one selected from a group consisting of carbon and hydrogen; and (c) after (b), etching the second region using a second plasma generated from a second processing gas different from the first processing gas.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes: providing a first process gas including oxygen and a second process gas including carbon and fluorine to a process chamber at a first flow rate ratio to etch an etch target layer; and providing the first process gas and the second process gas to the process chamber at a second flow rate ratio to passivate the etch target layer, wherein a flow rate of the first process gas is substantially constant.