Patent classifications
H01L21/31116
Isolation structures for semiconductor devices
A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.
Combined RF generator and RF solid-state matching network
In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source has an RF source control circuit carrying out a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The matching network provides a notice signal to the RF source indicating the VRE will be altered. In response to the notice signal, the RF source control circuit alters the power control scheme. While the power control scheme is altered, the VRE is altered to the new position.
CLEANING METHOD AND PLASMA PROCESSING APPARATUS
A substrate cleaning method includes: providing a substrate including a low-k layer containing silicon to a substrate support; etching the low-k layer by a plasma generated from a first gas; separating the etched substrate from the substrate support; and removing a reaction product attached to the substrate in the etching by a plasma generated from a second gas. The second gas includes a first carbon-containing gas represented by C.sub.xH.sub.yF.sub.z (y≥0, x/z>¼).
ETCHING METHOD AND ETCHING APPARATUS
An etching method includes preparing a substrate in which titanium nitride and molybdenum or tungsten are present, and etching the titanium nitride by supplying a processing gas including a ClF.sub.3 gas and a N.sub.2 gas to the substrate, wherein in the etching the titanium nitride, a partial pressure ratio of the ClF.sub.3 gas to the N.sub.2 gas in the processing gas is set to a value at which grain boundaries of the molybdenum or the tungsten are nitrided to such an extent that generation of a pitting is suppressed.
SACRIFICIAL CAPPING LAYER FOR CONTACT ETCH
A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.
Semiconductor device and method for manufacturing same
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
Semiconductor device having fins
A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.
Method of making a semiconductor device including etching of a metal silicate using sequential and cyclic application of reactive gases
A semiconductor manufacturing apparatus includes: a stage installed inside a processing chamber and holding a semiconductor substrate having a high-k insulating film including silicate; and a gas supply line including a first system supplying reactive gas to the processing chamber and a second system supplying catalytic gas to the processing chamber, wherein mixed gas which includes complex forming gas reacting with a metal element included in the high-k insulating film to form a first volatile organometallic complex and complex stabilizing material gas increasing stability of the first organometallic complex is supplied as the reactive gas, and catalytic gas using a second organometallic complex, which modifies the high-k insulating film and promotes a formation reaction of the first organometallic complex, as a raw material is supplied.
Semiconductor processing chamber multistage mixing apparatus
Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.
Capacitively coupled plasma etching apparatus
Disclosed is a capacitively coupled plasma etching apparatus, wherein an electrically conductive supporting rod where a lower electrode is fixed is connected to driving means, the driving means driving the electrically conductive support rod to move axially; besides, the lower electrode is fixed to the bottom of a chamber body via a retractable sealing part, causing the upper surface of the lower electrode to be hermetically sealed in an accommodation space in the chamber body; an electrical connection part is connected on the chamber body; the radio frequency current in the chamber body returns, via the electrical connection part, to the loop end of a radio frequency matcher. In this way, the lower electrode is fixed on the chamber body via the retractable sealing part, such that when the lower electrode is driven by the driving means to move up/down, the chamber body does not move along with it, and the radio frequency loop in the chamber body is in a steady state, thereby achieving stability of the radio frequency loop while implementing adjustability of the plate distance.